Recently in the internet there is much buzz about 3D stacking and in particular 3D NAND stacking with the upcoming revolution in the flash memory market with the mass adoption of this technology by all the major players.
One of the major companies involved is Applied Materials, a giant company based in the Santa Clara, California, US, founded in 1967 and with a long history of innovations in materials and processes for the semiconductor industry.
While there is much optimism in the industry for 3D stacking, still few major obstacles remain to solve before the technology is cleared for volume production.
3D stacking technology is very different from another technology that also includes the letters “3D” in its name, that is, 3D FinFet technology, but with FinFets we are talking about a different shape of the transistor while with 3D stacking we are instead talking about materially stacking layers one over the other
Many different ways of stacking has been explored so far, some of them involving patterning an entire wafer and then “folding” it once or many times so that one side is over the other, other techniques involve patterning two or more wafers and then bonding them together to create a single structure.
While 3D stacking can be done in many ways, the main issues at the core of the technology are the same: how to align multiple layers of transistor or cells with the adjacent ones, how to create vias so that each layer can communicate and delivery information electrically to the others.
Since complex structures may require to stack up to 32 layers one over the other, it is quite clear that the issues involved can become very complex as soon as more and more layers are added to the structure.
So far, viable solutions to 3D stacking for ICs have been found for NAND flash cells, with several companies such as SanDisk, Samsung and others already offering 3D NAND products to consumers, while 3D stacking for logic is still few years away, according to analysts.
Still, several solutions have been proposed to overcome problems with stacked 3D NANDs and ICs as well. One of the major problems seems to be how to get signals on and off the structure, since it is not possible to use the classic solution of just putting a contact on top of each cell as you would do with planar flash.
A proposed solution is about creating a “staircase-like” structure where the area of the layers at the bottom of each structure is slightly and by a few microns in diameter larger than the area of the layer immediately above, therefore leaving some areas at the edge of each layer unexposed and free to be connected by a contact.
However, creating such a structure is very challenging as it requires to etch every layer in a different way, with high precision and with very little room for error and then create the necessary contact structure with different contact points for every layer. This amounts to a series of challenges mostly new for the whole industry. [To be continued]
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