Current status of EUV lithography

It is undeniable that extreme ultra-violet lithography has progressed in an extraordinary way in the last 12 months.

Until recently, it was not commonly agreed upon in the lithography industry whether EUV litho would have made it to full production or HVM (high-volume manufacturing) at all.

Naysayers were pointing to the fact that the power of the light source was lagging much behind the level needed for HVM and that the issues in mask defectivity control and in resist development were far from being addressed properly.

Fortunately enough, in the last 12 months huge progress has been made in most if not all areas of EUV litho:

1. Light source development

Most of EUV pundits believe that light source power is the single most important issue for successful EUV lithography development and most resource investment related to EUCV has been focused in achieving a light source powerful enough to sustain high-volume manufacturing requirements.

Only one year ago, TSMC was having problems in breaking the 10W barrier while now the same company made public their results and claimed they were able to achieve an impressive 1000 wafers processed in a single day with a 80W source.

The two major companies behind EUV light source development, Cymer and Gigaphoton, are both claiming to be on track to achieve a 125W power source by the end of this year with a 250W light source on the horizon for next year.

Cymer claims to have a 100W power source running in their labs with 3.5% conversion efficiency and based on a 15KW laser which they hope to be able to upgrade to 5.5% conversion efficiency using a 27KW laser by next year at latest, which would mean 250W of light source power, well enough for high volume manufacturing

Gigaphoton, on the other hand, recently issued a press release announcing to have a light-source running at 142W with 50% duty cycle (=71W at 100% duty cycle), a significant improvement from last December when they claimed to have a 120W working at 50% duty cycle. Gigaphoton made clear that they are now looking for achieving 250W in “burst mode” before being able to expand the source availability.

While neither Gigaphoton nor Cymer have any plans for light sources beyond the 500W mark, Free Electron Lasers are now being considered by other players as a viable route to step into the 500W~10000W range which is what will be needed for high-NA scanner machines.

2. High-NA scanners

Carl Zeiss is currently working on improving the optics quality and based on this, ASML is now hoping to be able to achieve numerical aperture (NA) of 0.5 up from the current mark of 0.33 which would allow to reach a couple of nodes beyond 10nm without the need of multiple patterning using EUV.

3. Resists

Resist development has been an issue mostly disregarded by EUV pundits until recently as all the attention went to what was considered as the major hurdle for full development of EUV litho, that is, the availability of a light source powerful enough for HVM.

Since now the problems with light source development seem to be on track to be solved, attention is back to other aspects of EUV litho development such as resist.

Due to strict requirements it takes quite some time, even 1~3 years at least, to have a resist validated for full production so it has now become imperative to address this issue as well.

Much of the recent work is now behind negative-tone CAR resists, while Intel is working with resist makers on HfO2-based resists trying to improve their shelf-life from the current range of few weeks to a few months or more.

The advantage of metal oxide-based resists is that they have high absorption properties and therefore they can allow the use of light sources with lower power.

Other areas of development where control in EUV mask defectivity, with Hoya showing promising results in reducing the mask blank defects, and mask defect inspection, with Carl Zeiss announcing their upcoming tool specifically targeted at EUV mask inspection by the end of this year .

IBM’s EUV System Exceeds Target Output at 637 Wafers / Day

IBM has recently reported that their latest ASML extreme ultraviolet (EUV) lithography scanner system, NXE3300B, has produced 637 wafers in its first 24 hours of operation using a 44 watt light source at a rate of 34 wafers per hour, exceeding their target throughput of 500 wafers per day.

EUV is considered as the next generation technology for lithography scanners that will make the continuation of Moore’s law possible. As predicted by Moore’s law, the amount of transistors that can fit in a chip at a reasonable cost will double every two years. And the industry is now looking at EUV as the primary printing solution for finer patterns of smaller and denser chips.

However, even at the rate of IBM’s EUV scanner, it will still be difficult for the industry to continually shrink the transistors in a chip.  This technology will still be under research due to a couple of challenges. One of which is the weak light source, limiting the system from reaching the throughput requirement of at least 100 wafers per hour for mass volume production. Such throughput needs about 250 watts of light. Dan Corliss, IBM program manager for EUV development, said that they [IBM] are hoping to get an 80 watts of light source from ASML in about six months.

Comparing with the previous EUV systems of IBM and ASML which produced 7 and 14 wafers per day, respectively, this latest result of 637 wafers in a day is definitely a pleasant surprise for both IBM and ASML. Corliss’ team has been working on the EUV technology for 12 years. They had been calibrating the NXE3300B scanner for two months, which was initially delivered with only 25 watts of light source.

During the first tests, the system experienced interruptions along the way and the scanner was only up for about 77% of the time delivering 20 milliJoules across 83 pattern fields per wafer. Corliss estimated that without those interruptions, they would have produced more than 800 wafers in a day. The team is looking at the intermittent availability of the light source, and other issues with the system like mask defects.

In parallel to the EUV research activity in IBM, ASML is also working on pellicle development.  Pellicle is the filter used in immersion scanners and the manufacturers of ICs have been wanting it on their EUV systems too. Once ASML successfully emerge pellicle in EUV systems, the industry will surely benefit from this.

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The role of Applied Materials in the upcoming 3D stacking revolution (part 2)

3D stacking

So where Applied Materials see their strength in this process?

One of the areas where Applied Materials can work well with is the creation of the structure itself as the requirement for high precision manufacturing of the staircase structure leaves, as said, very little room for error. While an inferior process may lower the yield of a planar structure of just one or two percentage points, the same inferior process may lower the overall yield of a 16 or 32-layered structure considerably.

Another advantage for Applied Materials with 3D stacking is that the lithography part of the equation, while still important, is somehow less crucial to the final result as a 3D stacked structure built with 45nm lithography technology may have similar performance than a planar structure built with 22nm lithography. This would be good news for Applied Materials, who has more control on the etching and stacking side of the process and less control on the lithography and patterning side.

However, a loosening on tolerances on the lithography part comes with stricter tolerances on the etching part due to the precision needed to align and etch each layer: but here is where Applied Materials believes to have a competitive edge over other companies

One of the areas where Applied Materials claims to be able to offer improvements to the current process is with high aspect ratio etching. With 3D stacked ICs it is necessary to etch vias with aspect ratio up to 70:1 or higher, but problems of charged particles need to be carefully controlled on this regard.

New technological improvements such as the ability to control source and bias of the etching machine are aimed to solve the problem of charge particles which could make the creation of straight vias impossible. In addition to this, another improvement is the ability to etch separate layers without having to load and upload the wafers in between, are claimed to be real breakthroughs aimed at bring forward 3D stacking to IC manufacturing.

But etching vias with high aspect ratio is not the only issue: being able to etch them fast enough is also a must. This means that it is necessary to apply top layers with high selectivity and thick enough so that the underlying layers will be etched fast and deep enough. Moreover, a highly anisotropic process is needed.

Lack of high selectivity would mean that the mask layer would have to be very thick to be able to etch deep enough and this may result in impractically thick mask layers. Lack of a highly anisotropic process would mean side walls not vertical enough to be able to reach the required depth for the vias.

Another potential show stopper is the requirement of strict tolerances with thin film thickness and therefore ability to be able to deposit layers with less than one percent variation in thickness along the whole surface of the wafer and among different layers of the same structure is critical.

In conclusion, creation of 3D structures involves many more steps than simply exposure, develop, etch and resist removal. In addition to this, focus in the process moves away from the sole lithography as other steps of the process, namely deposition and etching, become critical. It remains to be seen if Applied Materials and the other big guys involved in the industry will be able to deliver the new solutions that are needed to move from planar to 3D ICs, still going 3D may be the only way for the whole semiconductory industry to keep pace with the continuous trend of increase in performance for ICs due to the numerous delays that have affected EUV and other litho technologies that were supposed to extend Moore` s Law life until the 2020s at earliest.

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The role of Applied Materials in the upcoming 3D stacking revolution (part 1)

3D stacking

Recently in the internet there is much buzz about 3D stacking and in particular 3D NAND stacking with the upcoming revolution in the flash memory market with the mass adoption of this technology by all the major players.

One of the major companies involved is Applied Materials, a giant company based in the Santa Clara, California, US, founded in 1967 and with a long history of innovations in materials and processes for the semiconductor industry.

While there is much optimism in the industry for 3D stacking, still few major obstacles remain to solve before the technology is cleared for volume production.

3D stacking technology is very different from another technology that also includes the letters 3D in its name, that is, 3D FinFet technology, but with FinFets we are talking about a different shape of the transistor while with 3D stacking we are instead talking about materially stacking layers one over the other

Many different ways of stacking has been explored so far, some of them involving patterning an entire wafer and then folding it once or many times so that one side is over the other, other techniques involve patterning two or more wafers and then bonding them together to create a single structure.

While 3D stacking can be done in many ways, the main issues at the core of the technology are the same: how to align multiple layers of transistor or cells with the adjacent ones, how to create vias so that each layer can communicate and delivery information electrically to the others.

Since complex structures may require to stack up to 32 layers one over the other, it is quite clear that the issues involved can become very complex as soon as more and more layers are added to the structure.

So far, viable solutions to 3D stacking for ICs have been found for NAND flash cells, with several companies such as SanDisk, Samsung and others already offering 3D NAND products to consumers, while 3D stacking for logic is still few years away, according to analysts.

Still, several solutions have been proposed to overcome problems with stacked 3D NANDs and ICs as well. One of the major problems seems to be how to get signals on and off the structure, since it is not possible to use the classic solution of just putting a contact on top of each cell as you would do with planar flash.

A proposed solution is about creating a staircase-like structure where the area of the layers at the bottom of each structure is slightly and by a few microns in diameter larger than the area of the layer immediately above, therefore leaving some areas at the edge of each layer unexposed and free to be connected by a contact.

However, creating such a structure is very challenging as it requires to etch every layer in a different way, with high precision and with very little room for error and then create the necessary contact structure with different contact points for every layer. This amounts to a series of challenges mostly new for the whole industry. [To be continued]

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Is it the end of Moore` s Law? (part 2)

Moore ` Law

At first, we need to ask ourselves why Moore` s Law should continue and what would be the possible future applications of ICs with tens or hundreds of times the computing power of today.

The current wave of smartphones and tablets already makes use of increasing quantities of raw computing power, but, according to analysts, many new applications are waiting out there: the “internet of things” buzz is now becoming louder.

The idea that buildings, roads, infrastructure, planes, cars could be all interconnected together to create a new virtual universe where all conditions and parameters can be monitored 24/7/365 is here and will require an enormous amount of computing power and new forms of integration of logic and analog into a single die.

MEMS (or micro-mechanical systems) are systems that integrate logic and analog circuitry into one single die and are already being developed and produced in industrial quantities right now but their scope of application is still limited to the gaming, automobile, medical and few other markets.

A new paradigm shift is needed before this concept can be applied to a broader range of infrastructure, however the building blocks are already here. As for the requirements in increase of computing power that such “internet of things” is likely to demand, the currently die-shrinking approach is likely to bring us only so far.

While the current scaling may continue for at least another 5 to 10 years, once the half-pitch will be in the whereabouts of 7nm to 5nm there will probably be no way to move forward with the current CMOS technology and alternatives such as nanotubes, new materials like graphene, completely new approaches to scaling like spintronics and 3D stacking are currently being explored.

Each one of the above alternatives holds enormous potential for the future of ICs.

Nanotubes can be fabricated at dimensions of few nanometers, graphene-manufactured ICs have less thermal issues than silicon and therefore can be stacked more easily and can reach frequencies of hundreds of GHzs.

Spintronics is a completely revolutionary technology that uses the spin of electrons instead of transistors to store and manipulate information

But in the shorter term, 3D stacking is the technology, or the family of technologies, that is more likely to bring some extra breathing room to Moore`s Law.

3D stacking is based on a simple idea: instead of keeping ICs as planar, they can be stacked one over the other therefore reducing the average distance between two points in the structure.

Currently, we are still at the beginning of this approach and the first applications in NAND stacking are being offered now.

3D stacking has quite some hurdles to be overcome, the main ones being thermal dissipation and the still high costs of TSVs (through silicon vias, that is the vias that are “bored” through the structure to allow communication between different planes)

At the moment 3D stacking is still in its infancy, but when it will be applied to ICs and SoC (system on chips) it will give additional breathe to Moore`s Law.

What will happen after that, remains to be seen.

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Is it the end of Moore` s Law? (part 1)

Moore ` Law

It is about twenty years, that is, since about when I started to become seriously interested in microelectronics and IC lithography, that I have heard this question from time to time: is Moore`s Law coming to an end?

And, if not then, until when will it last?

I still remember the old days in which researchers and “pundits” assured us that there would have been no way IC lithography could go beyond 0.1μm.

At first, let`s think what it would mean for the whole electronics industry if the current trend over continuous miniaturization of transistors would come to an end

Entire portions of the software industry and of the internet market have benefited, if not completely depended upon, the exponential growth of computing power we have witnessed in the last 40 years.

It is likely that such industries, along with others like the gaming industry, will be badly affected if Moore` s Law loses steam.

So, the question is: Is Moore` s Law anywhere close to the end?

From many points of view it is clear that the famous trend of keeping the number of circuits doubling every two years is becoming increasingly difficult and requires at every node a revolutionary, not just an evolutionary, approach as it happened in the recent past

A recent example of such radical innovations is the change from planar CMOS to FinFet architectures .

Even more recently, there has been much talk about moving away from silicon to overcome some of the major obstacles for further die shrinking and die stacking

Simple and brute force die shrinking is due to end soon as quantum tunneling is already starting to influence physical properties of transistors at the 10nm and would probably hinder any further progression at the 7nm node or 5nm node at best.

And even if, in principle, quantum tunneling effects could be included in the design of the IC so that they would not necessarily cause a disruption, simple economic considerations would put an halt to Moore` s Law.

Only one or two decades ago, a new state-of-the-art IC fab would have cost few hundreds of millions of US$, now we are in the range of US$4 billion for a new fab.

If the trend continues, we will soon be in the whereabouts of $10 billion per new fab. Very few governments, and no company, can invest such amount of money for a single fab. [to be continued]

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Nikon announces scanner for sub-10nm lithography

Direct self assembly

Japanese maker Nikon Corporation has introduced the new NSR-S630D ArF immersion scanner for patterning of IC chips at 10nm and below.

This news could be very important in an industry which is now moving from 14nm patterning to 10nm patterning and below in the next few years. Intel is already working on 10nm for its next generation of chips and beginning of production of 10nm IC components is scheduled for 2015.

Due to the increasing process complexities needed to transfer patterns of few tens of nanometers from the mask to the wafer, the industry has been exploring various options in the last two decades as it was widely believed until a few years ago that traditional stepper lithography would run out of gas around 90nm. The most prominent of such technologies is without doubt EUV, and most of the top-tier IC makers have invested billions in this technology. EUV technology is not employing a 193nm wavelength, but instead uses a much thinner 13.5-nm extreme ultra-violet light-source therefore allowing the patterning of much finer lines.

But while EUV has been plagued by numerous delays and it is now expected to reach maturity for high-volume production in a couple of years at the earliest, the life of traditional UV lithography has been extended thanks to numerous tweaks and fixes like multiple patterning and immersion which have helped the industry move from 90nm to the current generation of IC devices patterning at 14nm.

The new S630D stepper is part of the advanced Streamlign platform and delivers revolutionary solutions in order to extend the life of 193 nm immersion lithography until the 7nm node or possibly even up to the 5nm node, which is widely believed to be the end of traditional transistor scaling and the beginning of quantum-related nanotechnology.

Differently from EUV technology, where engineers are struggling to reach an output of 100 wafers/hours, Nikon has qualified their new scanner for HVM (high volume manufacturing) production at a whopping 250 wafer-per-hour efficiency. The new scanner is now able to achieve a resolution with is more than an order of magnitude finer than the wavelength of the laser used thanks to the improvements in reticle positioning accuracy and in thermal stress management. The new S630D is now able to reach a previously-unheard-of mix-and-match overlay (MMO) lower than 2.5nm and this means that the scanner is now able to meet most stringent requirements needed for multiple patterning with immersion.

The reason why such overlay requirements are so stringent is due to the fact that patterning such fine lines with a 193nm is like drawing a fine sketch using a broad brush. In order to achieve this, it is necessary to split all the patterning process into two, three or more masks and dedicate each single mask to a part of the whole patterning process. However, splitting the patterning process into multiple parts requires a strict overlay in order to avoid positioning errors between two subsequent exposures.

Hamid Zarringhalam, Nikon Precision Executive Vice President stated that his company is working hard to satisfy the device makers increasingly high demands for high-throughput production of IC devices at increasingly finer dimensions. Mr. Zharringalam believes that the key aspect of the new scanner offered by Nikon is the extremely accurate overlay control which reaches below 2.5nm and allows to bring multiple patterning to sub 10-nm patterning.

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