The role of Applied Materials in the upcoming 3D stacking revolution (part 2)

3D stacking

So where Applied Materials see their strength in this process?

One of the areas where Applied Materials can work well with is the creation of the structure itself as the requirement for high precision manufacturing of the staircase structure leaves, as said, very little room for error. While an inferior process may lower the yield of a planar structure of just one or two percentage points, the same inferior process may lower the overall yield of a 16 or 32-layered structure considerably.

Another advantage for Applied Materials with 3D stacking is that the lithography part of the equation, while still important, is somehow less crucial to the final result as a 3D stacked structure built with 45nm lithography technology may have similar performance than a planar structure built with 22nm lithography. This would be good news for Applied Materials, who has more control on the etching and stacking side of the process and less control on the lithography and patterning side.

However, a loosening on tolerances on the lithography part comes with stricter tolerances on the etching part due to the precision needed to align and etch each layer: but here is where Applied Materials believes to have a competitive edge over other companies

One of the areas where Applied Materials claims to be able to offer improvements to the current process is with high aspect ratio etching. With 3D stacked ICs it is necessary to etch vias with aspect ratio up to 70:1 or higher, but problems of charged particles need to be carefully controlled on this regard.

New technological improvements such as the ability to control source and bias of the etching machine are aimed to solve the problem of charge particles which could make the creation of straight vias impossible. In addition to this, another improvement is the ability to etch separate layers without having to load and upload the wafers in between, are claimed to be real breakthroughs aimed at bring forward 3D stacking to IC manufacturing.

But etching vias with high aspect ratio is not the only issue: being able to etch them fast enough is also a must. This means that it is necessary to apply top layers with high selectivity and thick enough so that the underlying layers will be etched fast and deep enough. Moreover, a highly anisotropic process is needed.

Lack of high selectivity would mean that the mask layer would have to be very thick to be able to etch deep enough and this may result in impractically thick mask layers. Lack of a highly anisotropic process would mean side walls not vertical enough to be able to reach the required depth for the vias.

Another potential show stopper is the requirement of strict tolerances with thin film thickness and therefore ability to be able to deposit layers with less than one percent variation in thickness along the whole surface of the wafer and among different layers of the same structure is critical.

In conclusion, creation of 3D structures involves many more steps than simply exposure, develop, etch and resist removal. In addition to this, focus in the process moves away from the sole lithography as other steps of the process, namely deposition and etching, become critical. It remains to be seen if Applied Materials and the other big guys involved in the industry will be able to deliver the new solutions that are needed to move from planar to 3D ICs, still going 3D may be the only way for the whole semiconductory industry to keep pace with the continuous trend of increase in performance for ICs due to the numerous delays that have affected EUV and other litho technologies that were supposed to extend Moore` s Law life until the 2020s at earliest.

If you are interested in our Nanoimprint lithography, please visit our Nanoimprint lithography service page.

Subscribe to our newsletter to receive our new articles directly in your mail box.

If you liked this article, please give it a quick review in StumbleUpon, Facebook or Pinterest.


The role of Applied Materials in the upcoming 3D stacking revolution (part 1)

3D stacking

Recently in the internet there is much buzz about 3D stacking and in particular 3D NAND stacking with the upcoming revolution in the flash memory market with the mass adoption of this technology by all the major players.

One of the major companies involved is Applied Materials, a giant company based in the Santa Clara, California, US, founded in 1967 and with a long history of innovations in materials and processes for the semiconductor industry.

While there is much optimism in the industry for 3D stacking, still few major obstacles remain to solve before the technology is cleared for volume production.

3D stacking technology is very different from another technology that also includes the letters 3D in its name, that is, 3D FinFet technology, but with FinFets we are talking about a different shape of the transistor while with 3D stacking we are instead talking about materially stacking layers one over the other

Many different ways of stacking has been explored so far, some of them involving patterning an entire wafer and then folding it once or many times so that one side is over the other, other techniques involve patterning two or more wafers and then bonding them together to create a single structure.

While 3D stacking can be done in many ways, the main issues at the core of the technology are the same: how to align multiple layers of transistor or cells with the adjacent ones, how to create vias so that each layer can communicate and delivery information electrically to the others.

Since complex structures may require to stack up to 32 layers one over the other, it is quite clear that the issues involved can become very complex as soon as more and more layers are added to the structure.

So far, viable solutions to 3D stacking for ICs have been found for NAND flash cells, with several companies such as SanDisk, Samsung and others already offering 3D NAND products to consumers, while 3D stacking for logic is still few years away, according to analysts.

Still, several solutions have been proposed to overcome problems with stacked 3D NANDs and ICs as well. One of the major problems seems to be how to get signals on and off the structure, since it is not possible to use the classic solution of just putting a contact on top of each cell as you would do with planar flash.

A proposed solution is about creating a staircase-like structure where the area of the layers at the bottom of each structure is slightly and by a few microns in diameter larger than the area of the layer immediately above, therefore leaving some areas at the edge of each layer unexposed and free to be connected by a contact.

However, creating such a structure is very challenging as it requires to etch every layer in a different way, with high precision and with very little room for error and then create the necessary contact structure with different contact points for every layer. This amounts to a series of challenges mostly new for the whole industry. [To be continued]

If you are interested in our Nanoimprint lithography, please visit our Nanoimprint lithography service page.

Subscribe to our newsletter to receive our new articles directly in your mail box.

If you liked this article, please give it a quick review in Stumbleupon, Facebook or Pinterest.


Is it the end of Moore` s Law? (part 2)

Moore ` Law

At first, we need to ask ourselves why Moore` s Law should continue and what would be the possible future applications of ICs with tens or hundreds of times the computing power of today.

The current wave of smartphones and tablets already makes use of increasing quantities of raw computing power, but, according to analysts, many new applications are waiting out there: the “internet of things” buzz is now becoming louder.

The idea that buildings, roads, infrastructure, planes, cars could be all interconnected together to create a new virtual universe where all conditions and parameters can be monitored 24/7/365 is here and will require an enormous amount of computing power and new forms of integration of logic and analog into a single die.

MEMS (or micro-mechanical systems) are systems that integrate logic and analog circuitry into one single die and are already being developed and produced in industrial quantities right now but their scope of application is still limited to the gaming, automobile, medical and few other markets.

A new paradigm shift is needed before this concept can be applied to a broader range of infrastructure, however the building blocks are already here. As for the requirements in increase of computing power that such “internet of things” is likely to demand, the currently die-shrinking approach is likely to bring us only so far.

While the current scaling may continue for at least another 5 to 10 years, once the half-pitch will be in the whereabouts of 7nm to 5nm there will probably be no way to move forward with the current CMOS technology and alternatives such as nanotubes, new materials like graphene, completely new approaches to scaling like spintronics and 3D stacking are currently being explored.

Each one of the above alternatives holds enormous potential for the future of ICs.

Nanotubes can be fabricated at dimensions of few nanometers, graphene-manufactured ICs have less thermal issues than silicon and therefore can be stacked more easily and can reach frequencies of hundreds of GHzs.

Spintronics is a completely revolutionary technology that uses the spin of electrons instead of transistors to store and manipulate information

But in the shorter term, 3D stacking is the technology, or the family of technologies, that is more likely to bring some extra breathing room to Moore`s Law.

3D stacking is based on a simple idea: instead of keeping ICs as planar, they can be stacked one over the other therefore reducing the average distance between two points in the structure.

Currently, we are still at the beginning of this approach and the first applications in NAND stacking are being offered now.

3D stacking has quite some hurdles to be overcome, the main ones being thermal dissipation and the still high costs of TSVs (through silicon vias, that is the vias that are “bored” through the structure to allow communication between different planes)

At the moment 3D stacking is still in its infancy, but when it will be applied to ICs and SoC (system on chips) it will give additional breathe to Moore`s Law.

What will happen after that, remains to be seen.

If you are interested in our services, please visit our site.

Subscribe to our newsletter to receive our new articles directly in your mail box.

If you liked this article, please give it a quick review in StumbleUpon, Facebook or Pinterest.

Is it the end of Moore` s Law? (part 1)

Moore ` Law

It is about twenty years, that is, since about when I started to become seriously interested in microelectronics and IC lithography, that I have heard this question from time to time: is Moore`s Law coming to an end?

And, if not then, until when will it last?

I still remember the old days in which researchers and “pundits” assured us that there would have been no way IC lithography could go beyond 0.1μm.

At first, let`s think what it would mean for the whole electronics industry if the current trend over continuous miniaturization of transistors would come to an end

Entire portions of the software industry and of the internet market have benefited, if not completely depended upon, the exponential growth of computing power we have witnessed in the last 40 years.

It is likely that such industries, along with others like the gaming industry, will be badly affected if Moore` s Law loses steam.

So, the question is: Is Moore` s Law anywhere close to the end?

From many points of view it is clear that the famous trend of keeping the number of circuits doubling every two years is becoming increasingly difficult and requires at every node a revolutionary, not just an evolutionary, approach as it happened in the recent past

A recent example of such radical innovations is the change from planar CMOS to FinFet architectures .

Even more recently, there has been much talk about moving away from silicon to overcome some of the major obstacles for further die shrinking and die stacking

Simple and brute force die shrinking is due to end soon as quantum tunneling is already starting to influence physical properties of transistors at the 10nm and would probably hinder any further progression at the 7nm node or 5nm node at best.

And even if, in principle, quantum tunneling effects could be included in the design of the IC so that they would not necessarily cause a disruption, simple economic considerations would put an halt to Moore` s Law.

Only one or two decades ago, a new state-of-the-art IC fab would have cost few hundreds of millions of US$, now we are in the range of US$4 billion for a new fab.

If the trend continues, we will soon be in the whereabouts of $10 billion per new fab. Very few governments, and no company, can invest such amount of money for a single fab. [to be continued]

If you are interested in our services, please visit our site.

Subscribe to our newsletter to receive our new articles directly in your mail box.

If you liked this article, please give it a quick review in StumbleUpon, Facebook or Pinterest.