Laser Sputter Deposition

Laser sputter deposition is a thin film deposition technique for silicon wafers, which uses high-energy pulsed laser radiation to ablate or knock-off target molecules and deposit them as a thin film layer on a wafer substrate. This technique was first tried by Smith and Turner in 1965. Three years later, Breech and Cross wrote a paper on laser vaporization and atom excitation.

At that time, quality of laser sputter deposition was far behind than that of the layers deposited by other techniques like molecular beam epitaxy and chemical vapor deposition. In 1987 laser sputter deposition became an established technique when Dijkkamp and his group used laser deposition on high-temperature superconductors (YBa2Cu3O7). Their work marked the starting point for the industry to utilize laser sputter deposition for layers of high quality crystals.

Since then, all types of oxides, nitrides, or even the metallic systems, and polymers have been deposited through laser.

How does laser sputter deposition work?

In laser sputter deposition, the target material undergoes a number of energy conversions before it is deposited on the substrate. First, when the radiated laser pulse hits the target, the energy is transferred as an electronic excitation, and then converted to thermal, chemical and mechanical energy.

All these energy conversions cause the target to evaporate, ablate, create plasma, and exfoliate.

The whole process can be divided in the following stages:

a.      Laser Sputtering of the Target Material

Laser sputtering uses a high-energy excimer laser pulse with very short wavelength like the KrF laser at 248nm. As the high-energy laser pulse is directed towards the target material causing energy transfer between the free electrons and the atoms. This will result in an extreme increase in temperature and in the evaporation of a part of the target.

 b.      Expansion of Material through Plasma

The vaporized material will expand towards the substrate in the plasma located in parallel to the target material. This expansion is dependent on the background pressure. An increase in background pressure slows down the excited particles, providing a higher chance for the deposited material to resputter. Thus, the deposition rate will decrease and material’s stoichiometry will be altered.

 c.       Deposition of the Sputtered Particles

Once the sputtered particles start bombarding the substrate surface, they will cause some of the substrate’s atoms to be knocked-off of its surface. Deposition begins when the condensation rate, caused by the collision of the sputtered particles of the target material and the substrate, is high enough to obtain thermal equilibrium.  It is important to have of continuous flow of sputtered particles to maintain thermal equilibrium.

d.      Growth of the Deposited Material

There are three growth techniques that can be used in laser sputter deposition: step flow, layer by layer, and 3D growth. In step flow growth, once the atoms of the target material reach the substrate surface, they will diffuse. Step flow growth is usually used on substrates with high crystal miscuts since the atomic steps on the substrate surface are formed from miscuts on the crystal.

Layer-by-layer technique, on the other hand, continuously grows islands of material until the islands overlap each other, a phenomenon known as coalescence. During coalescence, there is a huge density of material on the crater of the substrate surface. This whole process is performed for every additional layer.

In 3D growth mode, islands of material are formed on top of each other. This technique is somehow similar to layer-by-layer except for the fact that the deposition does not appear in a layered fashion because materials roughen every time it is added on top of the island.

Growth Modes for Laser Sputter Deposition

Figure 1. Growth Modes for Laser Sputter Deposition: (a) Step Flow, (b) Layer-by-layer, (c) 3D Growth.

The Characteristics of Laser Sputter Deposition

In comparison with other deposition techniques, laser sputter deposition is much more flexible as shown by the following parameters:

Target Size

Since the target size of the laser beam on laser sputter deposition is small, it is possible for this technique to deposit complex compounds. Such capability is usually useful for research purposes, especially when the preparation for the target material using other techniques would be expensive, like in the case of superconductor films.

Target Material Type

A deposition process with different types of target material must be operated in an ultra high vacuum chamber with the laser source located outside the chamber.  Some of the materials that can be prepared using laser sputter deposition are listed in Table 1.

Material Type Compound Reference
High-temperature superconductors YBa2Cu3O7




Dijkkamp (1987)

Guarnieri (1988)

Foster (1990)

Shinde (2001)

Oxides SiO2 Fogarassy (1990)
Carbides SiC Balooch (1990)
Nitrides TiN Biunno (1989)
Ferroelectric materials Pb(Zr,Ti)O3 Kidoh (1991)
Diamond-like carbon C Martin (1990)
Buckminster fullerene C60 Curl and Smalley (1991)
Polymers Polyethylene, PMMA Hansen and Robitaille (1988)
Metallic systems 30 alloys/multilayer


Krebs and Bremert (1993)

Geurtsen (1996)

Table 1. Some of the materials prepared for the first time by laser sputter deposition.

The Pulsed Nature of Laser

Some complex compounds such as polymer-metals require different multilayered conditions for the deposition of each component. One example is the deposition of polycarbonate silver. This kind of deposition is not possible with other techniques because of the big gap between the energy requirements of the two components. But with laser sputter deposition, the pulsed nature of the laser allows the polycarbonates to be deposited at low laser fluence of 60mJ/cm2 and the silver crystals at much higher laser fluence, about 80 times higher at 5J/cm2.


With the continuous advancements in laser technology, laser sputter deposition has emerged in the industry as a competitive technique for depositing thin films of complex stoichiometry but because of the small target size usable, it is not practical for large-scale layer formation.

Deposition Rate of Chemical Vapor Deposition

Chemical Vapor Deposition (CVD) is the process used to deposit thin film of solid material in various applications like fabrications of novel powder, fiber, preforms of ceramic composites, coatings for corrosion and wear resistance, and synthetic diamond. It is the most widely used technique in IC microfabrication for the oxide and nitride layers of the wafers. CVD process grows the film by chemically combining the material to an organic reactant and transports the chemical precursor to the target surface, which is energized either through heat, ion, or photon. The energy in the target drives the chemical reaction between the surface and the precursor to break the chemical precursor and incorporate the material to the growing film on the surface. (see Reaction Mechanisms of Chemical Vapor Deposition)

Reaction-Rate Limited Deposition

The two factors which affect the rate of film growth or the flux of the material in a CVD process are gas diffusion and surface process. As defined by Fick’s Law, the material’s flux to the substrate is a function of gas diffusion coefficient, concentration gradient of the layer, length of the surface for that will be deposited, and Reynold’s number – a dimensionless gas constant. Mathematically, the flux of the material is

 Fl = D Δc/2L 3√(Re           Equation 1

Since Reynold’s number is directly proportional to gas velocity, film growth rate is, therefore, also dependent on the square root of gas velocity. Moreover, gas velocity and gas flow rate is proportional to each other in a fixed volume reaction chamber.  Thus, film growth rate can be expressed as a function of gas flow rate, which is outlined in figure 1. The plot manifests the square root dependence of growth rate on flow rate as the former logarithmically increases with the latter.

However, there is a point where the growth rate saturates and becomes independent of the flow rate, which means no matter how much the flow rate is increased it cannot anymore affect the film growth rate. Once this happens, reaction rate takes over the control on deposition as demonstrated in the reaction-rate limited regime or the Arrhenius plot in figure 2 where growth rate is exponentially dependent on temperature. For a thermally driven surface reaction, the film growth rate can be mathematically modeled by:

R = Roe-Ea ⁄ kT            Equation 2


Ro is the frequency factor

Ea is the activation energy in electron Volt (eV), which is presumed to be approximately equal to the slope of the Arrhenius plot in Figure 2

T is temperature in Kelvin (K)

Film growth rate as a function of gas flow rate

Figure 1. Film growth rate as a function of gas flow rate (photo courtesy of book title here)

Film growth rate as a function of temperature

Figure 2. Film growth rate as a function of temperature (photo courtesy of book title here)

Vertical and Horizontal Wafer Stacking

Figure 3. Vertical and Horizontal Wafer Stacking (photo courtesy of book title here)

In a practical application, reaction-rate limited allows low pressure chemical vapor deposition (LPCVD) to stack the wafers vertically with very minimal spacing in between since the rate of reactant transport holds lesser importance (see Figure 3).  The diffusivity, D, of the reactants in a LPCVD reactor of ~1 Torr is magnified to 1000 times than its value at atmospheric pressure, which increases the arrival rate of the reactants to the substrate to one order of its current magnitude. Thus, the rate limiting step dominates the surface reaction control.

Mass-Transport Limited Deposition

On the other half of figure 2, excessive increase in temperature banishes the effect of reaction rate on the growth rate. At this regime, reaction rate cannot exceed anymore the rate at which the reactant gases are transported on the surface, no matter how high the temperature is. For this phase of rate-limiting reaction, which is known as the mass-transport limited deposition, growth rate is approximately equal to the square root of gas velocity.

Aside from the derived flux equation from Fick’s law (equation 1), the flux of the material, without considering its diffusion through the layer, can also be expressed as

Fl = h(CG-CS)          Equation 3


h is the mass transfer coefficient

CG is the reactant concentration at bulk of gas and

CS is the reactant concentration at substrate surface.

Moreover, the mass transport on a motionless layer in a CVD process is deduced to proceed by diffusion. Mathematically, this assumption is

Fl = D ( (CG-CS) / δ)          Equation 4

Equating equations 3 and 4, yields to

h (CG-CS) = D ( (CG-CS) / δ)

h = D / δ          Equation 5

For mass-transfer limited deposition D = 1. Thus, growth rate in this regime is

R = h = 1/δ = √U          Equation 6

Unlike in the reaction-rate limited regime where temperature owns the main control on growth rate, temperature is less important in mass-transport limited since its level does not limit the deposition rate. Applications for mass-transport limited like the atmospheric pressure chemical vapor deposition (APCVD) operate with the wafers stacked horizontally such that the flux of the reactant species is equally distributed to every corner of the wafer as well as of the other wafers.

Flow Stability

Uniform deposition requires stability of the flow in a CVD reaction chamber, which greatly depends on its laminar development before reaching the susceptor. As predicted by Schlichting, the flow entrance length for a full velocity profile is given by the equation

IF = 0.04HRe          Equation 7


H is height of the flow channel

Re is Reynold’s number

However, the thermal entrance length for a fully developed radial profile is seven times longer than its velocity entrance length.

IF = 0.28HRe          Equation 8

The characteristic of the flow of the gaseous reactants in a CVD process can be measured through a dimensionless gas constant known as Knudsen number (Kn). Knudsen number is defined as the ratio of the average distance that a molecule travels before colliding with another molecule or the molecular mean free path (λ) to the flow field length (L), which, in wafer fabrication’s case, is the size of the device structure. Knudsen number classifies the gas flow as:

  • continuum if Kn<0.01
  • slip if Kn is in between 0.01 and 0.1
  • transition if 0.1<Kn<10
  • free molecular for Kn>10

The reactant flow on the substrate usually falls on the transition or free molecular classification. As for the λ, the typical λ in a CVD process ranges from 0.1 microns to >100 microns at 100 Torr. But since the trend for the integrated circuits is to shrink up to the nanometer range, the λ may not be enough to attain uniform thickness over the whole process. For the industry to overcome this challenge on uniformity, the dominance of the molecular flow must be maintained by operating on very low pressure chemical vapor deposition (VLPCVD).

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The role of Applied Materials in the upcoming 3D stacking revolution (part 2)

3D stacking

So where Applied Materials see their strength in this process?

One of the areas where Applied Materials can work well with is the creation of the structure itself as the requirement for high precision manufacturing of the staircase structure leaves, as said, very little room for error. While an inferior process may lower the yield of a planar structure of just one or two percentage points, the same inferior process may lower the overall yield of a 16 or 32-layered structure considerably.

Another advantage for Applied Materials with 3D stacking is that the lithography part of the equation, while still important, is somehow less crucial to the final result as a 3D stacked structure built with 45nm lithography technology may have similar performance than a planar structure built with 22nm lithography. This would be good news for Applied Materials, who has more control on the etching and stacking side of the process and less control on the lithography and patterning side.

However, a loosening on tolerances on the lithography part comes with stricter tolerances on the etching part due to the precision needed to align and etch each layer: but here is where Applied Materials believes to have a competitive edge over other companies

One of the areas where Applied Materials claims to be able to offer improvements to the current process is with high aspect ratio etching. With 3D stacked ICs it is necessary to etch vias with aspect ratio up to 70:1 or higher, but problems of charged particles need to be carefully controlled on this regard.

New technological improvements such as the ability to control source and bias of the etching machine are aimed to solve the problem of charge particles which could make the creation of straight vias impossible. In addition to this, another improvement is the ability to etch separate layers without having to load and upload the wafers in between, are claimed to be real breakthroughs aimed at bring forward 3D stacking to IC manufacturing.

But etching vias with high aspect ratio is not the only issue: being able to etch them fast enough is also a must. This means that it is necessary to apply top layers with high selectivity and thick enough so that the underlying layers will be etched fast and deep enough. Moreover, a highly anisotropic process is needed.

Lack of high selectivity would mean that the mask layer would have to be very thick to be able to etch deep enough and this may result in impractically thick mask layers. Lack of a highly anisotropic process would mean side walls not vertical enough to be able to reach the required depth for the vias.

Another potential show stopper is the requirement of strict tolerances with thin film thickness and therefore ability to be able to deposit layers with less than one percent variation in thickness along the whole surface of the wafer and among different layers of the same structure is critical.

In conclusion, creation of 3D structures involves many more steps than simply exposure, develop, etch and resist removal. In addition to this, focus in the process moves away from the sole lithography as other steps of the process, namely deposition and etching, become critical. It remains to be seen if Applied Materials and the other big guys involved in the industry will be able to deliver the new solutions that are needed to move from planar to 3D ICs, still going 3D may be the only way for the whole semiconductory industry to keep pace with the continuous trend of increase in performance for ICs due to the numerous delays that have affected EUV and other litho technologies that were supposed to extend Moore` s Law life until the 2020s at earliest.

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The role of Applied Materials in the upcoming 3D stacking revolution (part 1)

3D stacking

Recently in the internet there is much buzz about 3D stacking and in particular 3D NAND stacking with the upcoming revolution in the flash memory market with the mass adoption of this technology by all the major players.

One of the major companies involved is Applied Materials, a giant company based in the Santa Clara, California, US, founded in 1967 and with a long history of innovations in materials and processes for the semiconductor industry.

While there is much optimism in the industry for 3D stacking, still few major obstacles remain to solve before the technology is cleared for volume production.

3D stacking technology is very different from another technology that also includes the letters 3D in its name, that is, 3D FinFet technology, but with FinFets we are talking about a different shape of the transistor while with 3D stacking we are instead talking about materially stacking layers one over the other

Many different ways of stacking has been explored so far, some of them involving patterning an entire wafer and then folding it once or many times so that one side is over the other, other techniques involve patterning two or more wafers and then bonding them together to create a single structure.

While 3D stacking can be done in many ways, the main issues at the core of the technology are the same: how to align multiple layers of transistor or cells with the adjacent ones, how to create vias so that each layer can communicate and delivery information electrically to the others.

Since complex structures may require to stack up to 32 layers one over the other, it is quite clear that the issues involved can become very complex as soon as more and more layers are added to the structure.

So far, viable solutions to 3D stacking for ICs have been found for NAND flash cells, with several companies such as SanDisk, Samsung and others already offering 3D NAND products to consumers, while 3D stacking for logic is still few years away, according to analysts.

Still, several solutions have been proposed to overcome problems with stacked 3D NANDs and ICs as well. One of the major problems seems to be how to get signals on and off the structure, since it is not possible to use the classic solution of just putting a contact on top of each cell as you would do with planar flash.

A proposed solution is about creating a staircase-like structure where the area of the layers at the bottom of each structure is slightly and by a few microns in diameter larger than the area of the layer immediately above, therefore leaving some areas at the edge of each layer unexposed and free to be connected by a contact.

However, creating such a structure is very challenging as it requires to etch every layer in a different way, with high precision and with very little room for error and then create the necessary contact structure with different contact points for every layer. This amounts to a series of challenges mostly new for the whole industry. [To be continued]

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